Control gates may be found in integrated circuit components, such as non-volatile memory cells of flash memory devices and select transistors, such as field effect transistors, e.g., in memory arrays, etc. For example, a non-volatile memory cell, e.g., of a flash memory, such as a NAND flash memory, may include a one-transistor memory cell having a control gate. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge storage structures (e.g., floating gates or charge traps), e.g., capacitively coupled to a control gate, or other physical phenomena (e.g., phase change, resistance change, or polarization) determine the data value of each cell.
An array of memory cells of NAND flash memory may be arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select transistors, e.g., a source select transistor and a drain select transistor. Each source select transistor is connected to a source, while each drain select transistor is connected to a data line, such as column bit line. A “column” refers to a group of memory cells that are commonly coupled to a data line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line.
To meet the demand for higher capacity memories, designers continue to strive to increase memory density, i.e., the number of memory cells in a given area of an integrated circuit die. One way to increase the density of a memory device is to form stacked memory arrays, e.g., often referred to as three-dimensional memory arrays.
For example, some stacked memory arrays might include stacked memory elements, e.g., in the form of vertical strings of series-coupled memory cells (e.g., vertical NAND strings). That is, for example, a vertical string of series-coupled memory cells might be adjacent to a vertical semiconductor, such as a vertical semiconductor pillar, that may act as channel region for the vertical string of memory cells. For example, during operation of one or more memory cells of the string, a channel can be formed in the semiconductor.
The term “vertical” may be defined, for example, as a direction that is perpendicular to a base structure, such as a surface of an integrated circuit die. It should be recognized the term vertical takes into account variations from “exactly” vertical due to routine manufacturing and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term vertical.
A nonvolatile memory cell in a string of series-coupled nonvolatile memory cells may include a charge-storage structure that is capacitively coupled to a control gate (e.g., that may be coupled to or may form a portion of an access line) through a dielectric capacitance. For example, a dielectric (e.g., an inter-dielectric) may be between the control gate and the charge-storage structure.
Performance characteristics of the memory cell may depend on the capacitive coupling between the control gate and the charge-storage structure. For example, increasing the capacitive coupling between the control gate and the charge-storage structure can improve the performance of a memory cell. The capacitive coupling may be increased by increasing the surface area of the surface of the inter-dielectric in contact with the control gate and/or the charge-storage structure, for example. However, it may be difficult to increase the surface area without increasing the size of the memory cell, and thus the memory array.
A capacitive coupling across a gate dielectric between a control gate of a select transistor and the semiconductor that may act as channel region for the vertical string of memory cells might affect the performance characteristics. The capacitive coupling may be increased by increasing the surface area of the gate dielectric in contact with the control gate and/or the semiconductor, for example. However, it may be difficult to increase the surface area without increasing the size of the select transistor, and thus the memory array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing methods of forming control gates.